Ubuntu
x-loader package

Merge lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243 into lp:ubuntu/maverick/x-loader

  1. Maverick (10.10)
  2. fix-628243
  3. Merge into maverick
Proposed by Ricardo Salveti
Status: Merged
Merge reported by: Andrew Starr-Bochicchio
Merged at revision: not available
Proposed branch: lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243
Merge into: lp:ubuntu/maverick/x-loader
Diff against target: 264 lines (+244/-0)
3 files modified
debian/changelog (+7/-0)
debian/patches/series (+1/-0)
debian/patches/support_micron_and_numonyx_memory.patch (+236/-0)
To merge this branch: bzr merge lp:~rsalveti/ubuntu/maverick/x-loader/fix-628243
Reviewer Review Type Date Requested Status
Ubuntu Sponsors Pending
Review via email: mp+34325@code.launchpad.net

Description of the change

Just adding support_micron_and_numonyx_memory.patch to make x-loader work with Micron and Numonyx based Beagle xMs.

Patch is already x-loader upstream.

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Revision history for this message
Stefano Rivera (stefanor) wrote :

Looks good to me, but it's a main package, and thus beyond my sponsoring powers.

Revision history for this message
Andrew Starr-Bochicchio (andrewsomething) wrote :

Seems to have already been uploaded:

https://edge.launchpad.net/ubuntu/+source/x-loader/1.4.4git20100713-1ubuntu1

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=== modified file 'debian/changelog'
--- debian/changelog 2010-07-13 13:11:12 +0000
+++ debian/changelog 2010-09-01 18:11:45 +0000
@@ -1,3 +1,10 @@
1x-loader (1.4.4git20100713-1ubuntu1) maverick; urgency=low
2
3 * adding support_micron_and_numonyx_memory.patch to make x-loader
4 work with Micron and Numonyx based Beagle xMs (LP: #628243)
5
6 -- Ricardo Salveti de Araujo <ricardo.salveti@canonical.com> Wed, 01 Sep 2010 14:30:46 -0300
7
1x-loader (1.4.4git20100713-1) maverick; urgency=low8x-loader (1.4.4git20100713-1) maverick; urgency=low
29
3 * new upstream release 10 * new upstream release
411
=== modified file 'debian/patches/series'
--- debian/patches/series 2010-07-13 13:11:12 +0000
+++ debian/patches/series 2010-09-01 18:11:45 +0000
@@ -1,3 +1,4 @@
1no_cross_compile.diff1no_cross_compile.diff
2no_stack_protector.diff2no_stack_protector.diff
3add_signGP.diff3add_signGP.diff
4support_micron_and_numonyx_memory.patch
45
=== added file 'debian/patches/support_micron_and_numonyx_memory.patch'
--- debian/patches/support_micron_and_numonyx_memory.patch 1970-01-01 00:00:00 +0000
+++ debian/patches/support_micron_and_numonyx_memory.patch 2010-09-01 18:11:45 +0000
@@ -0,0 +1,236 @@
1From ead751e4a361ce19552ac94bbeba232f12849244 Mon Sep 17 00:00:00 2001
2From: Steve Kipisz <s-kipisz2@ti.com>
3Date: Thu, 8 Jul 2010 10:30:58 -0500
4Subject: [PATCH] Support Micron or Numonyx memory
5
6---
7 board/omap3530beagle/omap3530beagle.c | 56 +++++++++++++++++++++++++++-----
8 drivers/k9f1g08r0a.c | 43 +++++++++++++++++++------
9 include/asm/arch-omap3/mem.h | 43 ++++++++++++++++++++++++-
10 3 files changed, 121 insertions(+), 21 deletions(-)
11
12diff --git a/board/omap3530beagle/omap3530beagle.c b/board/omap3530beagle/omap3530beagle.c
13index eb8008e..1254aa0 100644
14--- a/board/omap3530beagle/omap3530beagle.c
15+++ b/board/omap3530beagle/omap3530beagle.c
16@@ -265,6 +265,32 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
17 }
18
19 #ifdef CFG_3430SDRAM_DDR
20+
21+#define MICRON_DDR 0
22+#define NUMONYX_MCP 1
23+int identify_xm_ddr()
24+{
25+ int mfr, id;
26+
27+ __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
28+ __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
29+ __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
30+ __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
31+ __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
32+ __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
33+
34+ /* Enable the GPMC Mapping */
35+ __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
36+ ((NAND_BASE_ADR>>24) & 0x3F) |
37+ (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
38+ delay(2000);
39+
40+ nand_readid(&mfr, &id);
41+ if (mfr == 0)
42+ return MICRON_DDR;
43+ if ((mfr == 0x20) && (id == 0xba))
44+ return NUMONYX_MCP;
45+}
46 /*********************************************************************
47 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
48 *********************************************************************/
49@@ -279,15 +305,27 @@ void config_3430sdram_ddr(void)
50 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
51
52 if (beagle_revision() == REVISION_XM) {
53- __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
54- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_0);
55- __raw_writel(SDP_SDRC_MDCFG_0_DDR_XM, SDRC_MCFG_1);
56- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
57- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
58- __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
59- __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
60- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
61- __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
62+ if (identify_xm_ddr() == MICRON_DDR) {
63+ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
64+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
65+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
66+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_0);
67+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_0);
68+ __raw_writel(MICRON_V_ACTIMA_200, SDRC_ACTIM_CTRLA_1);
69+ __raw_writel(MICRON_V_ACTIMB_200, SDRC_ACTIM_CTRLB_1);
70+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_0);
71+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_200MHz, SDRC_RFR_CTRL_1);
72+ } else {
73+ __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
74+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
75+ __raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
76+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
77+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
78+ __raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
79+ __raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
80+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
81+ __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
82+ }
83 } else {
84 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
85 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
86diff --git a/drivers/k9f1g08r0a.c b/drivers/k9f1g08r0a.c
87index 8968a1b..d2da804 100644
88--- a/drivers/k9f1g08r0a.c
89+++ b/drivers/k9f1g08r0a.c
90@@ -154,6 +154,29 @@ static int NanD_Address(unsigned int numbytes, unsigned long ofs)
91 return 0;
92 }
93
94+int nand_readid(int *mfr, int *id)
95+{
96+ NAND_ENABLE_CE();
97+
98+ if (NanD_Command(NAND_CMD_RESET)) {
99+ NAND_DISABLE_CE();
100+ return 1;
101+ }
102+
103+ if (NanD_Command(NAND_CMD_READID)) {
104+ NAND_DISABLE_CE();
105+ return 1;
106+ }
107+
108+ NanD_Address(ADDR_COLUMN, 0);
109+
110+ *mfr = READ_NAND(NAND_ADDR);
111+ *id = READ_NAND(NAND_ADDR);
112+
113+ NAND_DISABLE_CE();
114+ return 0;
115+}
116+
117 /* read chip mfr and id
118 * return 0 if they match board config
119 * return 1 if not
120@@ -162,23 +185,23 @@ int nand_chip()
121 {
122 int mfr, id;
123
124- NAND_ENABLE_CE();
125+ NAND_ENABLE_CE();
126
127- if (NanD_Command(NAND_CMD_RESET)) {
128- printf("Err: RESET\n");
129- NAND_DISABLE_CE();
130+ if (NanD_Command(NAND_CMD_RESET)) {
131+ printf("Err: RESET\n");
132+ NAND_DISABLE_CE();
133 return 1;
134 }
135
136- if (NanD_Command(NAND_CMD_READID)) {
137- printf("Err: READID\n");
138- NAND_DISABLE_CE();
139+ if (NanD_Command(NAND_CMD_READID)) {
140+ printf("Err: READID\n");
141+ NAND_DISABLE_CE();
142 return 1;
143- }
144+ }
145
146- NanD_Address(ADDR_COLUMN, 0);
147+ NanD_Address(ADDR_COLUMN, 0);
148
149- mfr = READ_NAND(NAND_ADDR);
150+ mfr = READ_NAND(NAND_ADDR);
151 id = READ_NAND(NAND_ADDR);
152
153 NAND_DISABLE_CE();
154diff --git a/include/asm/arch-omap3/mem.h b/include/asm/arch-omap3/mem.h
155index cba4c6f..63cdba1 100644
156--- a/include/asm/arch-omap3/mem.h
157+++ b/include/asm/arch-omap3/mem.h
158@@ -46,6 +46,7 @@ typedef enum {
159 #define MMC_NAND 4
160 #define MMC_ONENAND 5
161 #define GPMC_NONE 6
162+#define GPMC_ONENAND_TRY 7
163
164 #endif
165
166@@ -71,7 +72,8 @@ typedef enum {
167 #define SDP_SDRC_MDCFG_0_DDR (0x02582019|B_ALL) /* Infin ddr module */
168 #else
169 #define SDP_SDRC_MDCFG_0_DDR (0x02584019|B_ALL)
170-#define SDP_SDRC_MDCFG_0_DDR_XM (0x03588019|B_ALL)
171+#define SDP_SDRC_MDCFG_0_DDR_MICRON_XM (0x03588019|B_ALL)
172+#define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM (0x04590019|B_ALL)
173 #endif
174
175 #define SDP_SDRC_MR_0_DDR 0x00000032
176@@ -252,12 +254,47 @@ typedef enum {
177 (MICRON_TDPL_200 << 6) | (MICRON_TDAL_200))
178
179 #define MICRON_TWTR_200 2
180-#define MICRON_TCKE_200 1
181+#define MICRON_TCKE_200 4
182 #define MICRON_TXP_200 2
183 #define MICRON_XSR_200 23
184 #define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | (MICRON_XSR_200 << 0)) | \
185 (MICRON_TXP_200 << 8) | (MICRON_TWTR_200 << 16)
186
187+/* NUMONYX part of IGEP0020 (165MHz optimized) 6.06ns
188+ * ACTIMA
189+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
190+ * TDPL (Twr) = 15/6 = 2.5 -> 3
191+ * TRRD = 12/6 = 2
192+ * TRCD = 22.5/6 = 3.75 -> 4
193+ * TRP = 18/6 = 3
194+ * TRAS = 42/6 = 7
195+ * TRC = 60/6 = 10
196+ * TRFC = 140/6 = 23.3 -> 24
197+ * ACTIMB
198+ * TWTR = 2
199+ * TCKE = 2
200+ * TXSR = 200/6 = 33.3 -> 34
201+ * TXP = 1.0 + 1.1 = 2.1 -> 3 ¿?
202+ */
203+#define NUMONYX_TDAL_165 6
204+#define NUMONYX_TDPL_165 3
205+#define NUMONYX_TRRD_165 2
206+#define NUMONYX_TRCD_165 4
207+#define NUMONYX_TRP_165 3
208+#define NUMONYX_TRAS_165 7
209+#define NUMONYX_TRC_165 10
210+#define NUMONYX_TRFC_165 24
211+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) \
212+ | (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) |(NUMONYX_TRRD_165 << 9) | \
213+ (NUMONYX_TDPL_165 << 6) | (NUMONYX_TDAL_165))
214+
215+#define NUMONYX_TWTR_165 2
216+#define NUMONYX_TCKE_165 2
217+#define NUMONYX_TXP_165 3
218+#define NUMONYX_XSR_165 34
219+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
220+ (NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
221+
222 /* New and compatability speed defines */
223 #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
224 # define L3_100MHZ /* Use with <= 100MHz SDRAM */
225@@ -276,6 +313,8 @@ typedef enum {
226 #elif defined(L3_165MHZ)
227 # define MICRON_SDRC_ACTIM_CTRLA_0 MICRON_V_ACTIMA_165
228 # define MICRON_SDRC_ACTIM_CTRLB_0 MICRON_V_ACTIMB_165
229+# define NUMONYX_SDRC_ACTIM_CTRLA_0 NUMONYX_V_ACTIMA_165
230+# define NUMONYX_SDRC_ACTIM_CTRLB_0 NUMONYX_V_ACTIMB_165
231 #endif
232
233
234--
2351.7.1
236

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